Central processing units in all different types of computing devices continue to increase in operating speed, with similar gains occurring in peripheral circuits such as memories, peripheral computing interface (PCI) circuits, graphics processors, and many others. However, the gains in speed have begun to run into external physical limitations that hamper performance by capping the data transfer speed between the processor and its associated peripheral devices, including the memory. These limitations include signal integrity problems due to high capacitance/high resistance signal lines, tight line spacing on printed circuit boards which leads to crosstalk, connector and circuit trace discontinuities in the signal path, and increased power consumption leading to higher device temperatures and heat management problems. Dealing with these factors often results in lengthened, more expensive design cycles, more costly motherboard layout and production, and more complicated and costly cooling techniques.
One can view signal integrity as the measure of confidence that a data value received at one end of a signal line matches the data value transmitted from the other end. As the transmission speed increases, previously inconsequential circuit non-idealities such as cross-talk, line capacitance, and impedance discontinuities, have a greater impact on the signal fidelity, which limits the achievable speed to a level below that what the native semiconductor devices could otherwise support.
The number of elements within CPU and memory devices, and their native switching speed, has increased along the way to increasing processing speed, and the number of Input-Output (I/O) pins has similarly increased to provide wider data paths and, hence, transfer rate, to the outside world; however, the general package size remains the same or smaller. This results in more and more dense CPU connector pin arrays, which in turn forces the signal lines between external devices and the CPU to be placed closer and closer together. This leads to increased line-to-line coupling, resulting in greater cross-talk and reduced signal integrity.
Other characteristics associated with current architectures also contribute to reduced signal integrity. The push to increase memory capacity results in more and more memory devices being connected to the memory bus, often resulting in longer bus lengths to accommodate more memory modules. Longer lines, however, come at a price, which includes relatively high capacitance in the signal paths, relatively high series resistance of the signal paths, an increasing number of discontinuities in the signal path, and greater disparity in time delays between the driving end of the bus and the nearest and farthest load or destination devices.
In a typical memory array, precise synchronization of send and receive activities is vital to the proper overall operation. As more and more memory or other peripheral circuits or devices are connected along a bus, the disparity in the time delay between the CPU and the nearest destination or load device, and the CPU and the farthest destination or load device, becomes problematic. For proper synchronization, all devices must wait until certain signals have been received, thus limiting the speed of the entire network to that of the slowest (farthest away) device. Various techniques are used to attempt to mitigate this so-called differential delay problem, but in general, the longer the line the slower the overall performance.
The signal lines between the CPU and memory or other peripherals may be crafted as transmission lines having a specific line impedance, with driving and load end terminations, or as simple wires. Transmission lines generally provide the highest speed signal transmission environment, but the requirement that they be resistively terminated for proper signal integrity mandates the use of extra power supplies and termination resistors, and an attendant increase in power. If properly terminated an ideal transmission line can provide good signal fidelity independent of length; however, in the case of a memory system, each connection, or “Tap”, along the line, and the series resistance inherent in the wire itself, disrupt or attenuate the signal along the line and place a limit on the useful length at any given frequency of operation.
Signal lines may also be designed as simple wires, in which case they do not require termination; however, their performance is now limited by the series resistance of the metal, and the parasitic capacitance to ground and/or other nearby wires.
The series resistance in each signal line consumes a portion of the signal power present at the input end of the line, converting the electrical energy into heat and in the process attenuating the signal. The longer the line the greater the signal attenuation, until at some point the receiving end can no longer recognize the information encoded on the signal. This imposes limits on the length of the signal path, which will probably be different than in the case of a transmission line environment described above and, therefore, the overall size of the memory. Amplifiers, buffers, and repeaters may alleviate this issue, but these all contribute to increased overall component count and board area, increased power and thermal load, and increased cost and complexity of the system.
Signal lines crafted as simple wires are also sensitive to, and limited by, their capacitance to ground and surrounding conductors. As the length of the line increases, or the physical distance to ground or other conductors is reduced, or the number of taps increases, the line capacitance increases. Higher capacitance, coupled with higher resistance, results in lower signal path bandwidth, which in the case of a digital pulse train slows the rising and falling edges. As the edges slow the pulse stretches out in time, so fewer bits of data can be transmitted in a given interval and data transfer rate drops or become limited. As the pulse transmission rate is increased the data bits can run together resulting in errors due to so-called inter-symbol interference.
Discontinuities typically consist of transitions in the size and thickness of the metal or other conductive material forming the signal path. For example, a signal line transition to the contact pad of a through-via on a printed circuit board, a trace turning a corner, a signal line intersecting the contact pad for a memory connector, or for a pin on the ball grid array or land grid array on an integrated circuit, all cause discontinuities. These change the local impedance of a transmission line on the one hand, or add capacitance to a simple wire on the other hand, both of which distort the shape of the signal due to reflections or simply reduce the bandwidth and, hence, the amplitude. All of these effects impact the signal integrity, in turn leading to data errors that require compensation such as periodic retransmission of the signals, confirmation signaling, or other typical error correction approached.
One approach to handling signal integrity problems involves boosting the power of the signal to compensate for attenuation or distortion, resulting in higher power consumption for the CPU and the peripheral circuits. This also produces a higher level of heat to manage. Heat in general causes a degradation in the semiconductor devices due to increased current leakage within the transistors, as well as a general reduction in transistor operating speed due to decreased conductor mobility. This mitigation approach can result in a cycle of boosting the power to overcome the loss of speed, generating more heat because of the increased power, which then requires a further increase in power and heat, until one reaches a practical or economic limit.
Other error mitigation approaches involve reducing the speed of the transmissions, thereby reducing the impact of capacitive loading on the lines, as well as reducing the power required to drive the lines at higher speeds. However, this approach runs counter to the desire for faster speeds and more performance.
Still other mitigation approaches stack the memory chips and/or the processor chips to shorten the communication paths. However, these require custom designed motherboards and non-traditional system architectures, making them impractical for typically uses.